While a variety of materials configurations exist in integrate circuit structures, a common element for many integrated circuit structures is the dielectric-filled isolation trench. Isolation trenches are widely used to allow the compact arrangement of electrically active components making up the integrated circuit(s) without adverse effects on electrical operability.
When isolation trench structures are formed in a substrate (e.g., by etching), variation in trench depth often occurs between the various trenches formed on the same substrate level on different parts of the wafer. Typically, the variation may be on the order of about 10% of the intended trench depth. To ensure that all the trenches (across the entire wafer) are completely filled with dielectric isolation material, it is typically necessary to deposit sufficient dielectric material to account for the non-uniformity of trench depth.
The necessity to account for variation in trench depth results in an overfill of the shallower trenches and a fairly thick deposit over the wafer surface. Additionally, the dielectric material (typically an oxide) deposited to fill the trenches is typically conformal to some extent. Thus, the local step topography (step height) of the trenches is reflected at least to some extent in the upper surface of the dielectric deposited to fill the trenches. Large step height is normally encountered in combination with a high xe2x80x9cwithinxe2x80x9d wafer (overfill) thickness. The deeper (or more narrow the aspect ratio) the trench to be filled, the greater the step height in the dielectric filling layer and the more overfill is required to ensure complete filling of the trench structures across the wafer.
Another use of dielectric oxides, such as silicon oxides formed by reacting tetraethylorthosilicate (TEOS) and oxygen or ozone, is for so-called interlevel dielectric (ILD), e.g., between metal interconnects of aluminum/copper or tungsten typically for back end of the line (BEOL) wiring. A general discussion of interlevel dielectrics can be found in xe2x80x9cFundamentals of Semiconductor Processing Technologyxe2x80x9d by El- Kareh, Kluwer Academic Publishers, (1995), pages 565-571, which discussion is incorporated herein by reference. Silicon oxide layers and other insulators obtained by other processes may also be used as interlevel dielectrics. For example, other widely used materials for such purposes are boron and/or phosphorous doped silicate glasses.
In a formation of a conventional ILD oxide structure, a first layer of interlevel dielectric such as silicon oxide may be deposited on a surface having raised metal features (e.g., metal lines) by chemical vapor deposition (CVD) with the silicon oxide filling the gaps between the metal lines. This CVD step typically results in the formation of undesired voids between in the deposited oxide between the metal features. The silicon oxide over the horizontal (top) surfaces of the metal lines may then be removed by an anisotropic etch (e.g., sputter etching) to open the voids. The structure at this point typically has silicon oxide left in spaces between lines and as spacers on the sidewalls of the metal lines. A second layer of an insulator such as silicon oxide can then be deposited to fill the voids and complete the interlevel dielectric structure between different metallic layers.
Chemical-mechanical polishing (CMP) to remove dielectric materials has been widely used to improve the quality and manufacturability of integrated circuit device structures. Generally, the objective in polishing is to remove the deposited dielectric material across the wafer so it remains only within the trenches (or between conductive features, e.g., metal lines) and presents a planar surface for subsequent processing.
Often, a reactive ion etching process (to reduce step height and/or overall thickness in the deposited dielectric material) is required in combination with a conventional slurry chemical-mechanical polishing (CMP) process in order to obtain proper planarization. Reactive ion etch processes are not desirable from the point of cost and/or process control.
Conventional slurry-less CMP (alkaline mediumxe2x80x94pH=11xe2x80x94using a fixed abrasive) is generally selective to step height (i.e., capable of reducing step height differential), but where the step height differential is substantial, slurry-less CMP is not capable of performing the necessary material removal without over polishing which results in a non-planar final surface. This deficiency limits use of slurry-less CMP processes to structures with small (e.g., less than 200 xc3x85) variation in trench depth or oxide overfill.
Often in these various CMP processes, the need to stop on the underlayer (without overpolishing) may lead to the use of elaborate polishing endpoint detection techniques to avoid overpolishing. This concern is especially present for interlevel dielectrics where overpolishing may erode the metal or dish the fill oxide or compromise adjacent or underlying metal features. Concern regarding overpolishing may also lead to use of processes having slow polishing rates which result in increased process time.
Thus, there is a need for improve polishing processes which are capable of removing material at large step height differential to produce a substantially planar surface while avoiding the need for RIE etch back processing or other undesirable alternatives. There is also a need for improved polishing processes that enable more control against overpolishing.
The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even where the starting oxide layer has significant topographical variation (e.g., step height differential). The processes of the invention are preferably characterized by the use of a fixed abrasive polishing element and by use of an aqueous liquid medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide material on the substrate.
In one aspect, the invention encompasses a method of polishing an oxide material layer on a substrate by slurry-less chemical-mechanical polishing, the method comprising:
a) providing a substrate having an oxide material layer on a first surface, the oxide material layer having portions which have a height differential relative to each other, the height being measured from a reference plane parallel with a principal plane of the substrate,
b) providing an aqueous liquid medium containing a polyelectrolyte,
c) contacting the oxide material layer of the substrate with the aqueous liquid medium and with a polishing member, the polishing member containing a fixed abrasive component therein, and
d) maintaining the contact of step c) while providing movement between the substrate and polishing member, whereby the height differential becomes reduced.
The oxide material to be polished is preferably a dielectric material, more preferably silica or boron phosphosilicate glass (BPSG). The polyelectrolyte is preferably a polyacrylic acid. Preferably, step d) is conducted until an underlayer is revealed to a desired extent.
In another aspect, the invention encompasses a method for removing exposed interlevel dielectric oxide from a substrate, the method comprising
a) providing a substrate having at least one feature selected from the group consisting of (i) a metal or conductive metal-containing structure contacting an exposed oxide layer, and (ii) a metal or conductive metal-containing structure having an exposed surface in an exposed oxide material layer,
b) providing an aqueous liquid medium containing a polyelectrolyte,
c) contacting the oxide material layer of the substrate with the aqueous liquid medium and with a polishing member, the polishing member containing a fixed abrasive component therein, and
d) maintaining the contact of step c) while providing movement between the substrate and polishing member, whereby oxide material is removed.
In a further aspect, the invention encompasses the conducting of the slurry-less processes of the invention to a desired planarize endpoint without the use of a special endpoint detection technique. These and other aspects of the invention are described in further detail below.